This preview shows page 1. Sign up to view the full content.
Unformatted text preview: asked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. 3-246 Vol. 2 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
#SS(0) #GP(0) #PF(fault-code) #NM #MF #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-247 INSTRUCTION SET REFERENCE, A-M CVTTSD2SI--Convert with Truncation Scalar Double-Precision FloatingPoint Value to Signed Doubleword Integer
Opcode F2 0F 2C /r Instruction CVTTSD2SI r32, xmm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer in r32 using truncation. Convert one double precision floating-point value from xmm/m64 to one signed quadword integer in r64 using truncation. REX.W + F2 0F 2C /r CVTTSD2SI r64, xmm/m64 Valid N.E. Description
Converts a double-precision floating-point value in the source operand (second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a generalpurpose register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register. When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than the maximum signed doubleword integer, the floatingpoint invalid exception is raised. If this exception is masked, the indefinite integer value (80000000H) is returned. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits. Operation
IF 64-Bit Mode and OperandSize = 64 THEN DEST[63:0] Convert_Double_Precision_Floating_Point_To_ Integer_Truncate(SRC[63:0]); ELSE DEST[31:0] Convert_Double_Precision_Floating_Point_To_ Integer_Truncate(SRC[63:0]); FI; 3-248 Vol. 2 INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent
View Full Document
This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11