ia-32_instruction-set-ref_a-m

Is enabled and an unaligned memory reference is made

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Unformatted text preview: mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]); DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_ Truncate(SRC[127:64]); Intel C/C++ Compiler Intrinsic Equivalent CVTTPD1PI__m64 _mm_cvttpd_pi32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. 3-236 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #MF #NM #XM #UD For an illegal address in the SS segment. For a page fault. If there is a pending x87 FPU exception. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #MF #XM #UD If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Vol. 2 3-237 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-238 Vol. 2 INSTRUCTION SET REFERENCE, A-M CVTTPD2DQ--Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F E6 Instruction CVTTPD2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1 using truncation. Description Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location....
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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