ia-32_instruction-set-ref_a-m

Is enabled and an unaligned memory reference is made

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Unformatted text preview: tional instruction that uses the mask result in the destination operand as an input operand will not generate a fault, since a mask of all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN. Some of the comparisons listed in Table 3-7 can be achieved only through software emulation. For these comparisons the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination operand), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in Table 3-7 under the heading Emulation. Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPSS instruction. See Table 3-11. 3-144 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-11. Pseudo-Ops and CMPSS Pseudo-Op CMPEQSS xmm1, xmm2 CMPLTSS xmm1, xmm2 CMPLESS xmm1, xmm2 CMPUNORDSS xmm1, xmm2 CMPNEQSS xmm1, xmm2 CMPNLTSS xmm1, xmm2 CMPNLESS xmm1, xmm2 CMPORDSS xmm1, xmm2 CMPSS Implementation CMPSS xmm1, xmm2, 0 CMPSS xmm1, xmm2, 1 CMPSS xmm1, xmm2, 2 CMPSS xmm1, xmm2, 3 CMPSS xmm1, xmm2, 4 CMPSS xmm1, xmm2, 5 CMPSS xmm1, xmm2, 6 CMPSS xmm1, xmm2, 7 The greater-than relations not implemented in the processor require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.) In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation CASE (COMPARISON PREDICATE) OF 0: OP EQ; 1: OP LT; 2: OP LE; 3: OP UNORD; 4: OP NEQ; 5: OP NLT; 6: OP NLE; 7: OP ORD; DEFAULT: Reserved; CMP0 DEST[31:0] OP SRC[31:0]; IF CMP0 = TRUE THEN DEST[31:0] FFFFFFFFH; ELSE DEST[31:0] 00000000H; FI; (* DEST[127:32] unchanged *) Vol. 2 3-145 INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalents CMPSS for equality CMPSS for less-than CMPSS for less-than-or-equal CMPSS for greater-than CMPSS for inequality CMPSS for not-less-than CMPSS for not-greater-than CMPSS for ordered CMPSS for unordered __m128 _mm_cmpeq_ss(__m128 a, __m128 b) __m128 _mm_cmplt_ss(__m128 a, __m128 b) __m128 _mm_cmple_ss(__m128 a, __m128 b) __m128 _mm_cmpgt_ss(__m128 a, __m128 b) __m128 _mm_cmpneq_ss(__m128 a, __m128 b) __m128 _mm_cmpnlt_ss(__m128 a, __m128 b) __m128 _mm_cmpngt_ss(__m128 a, __m128 b) __m128 _mm_cmpord_ss(__m128 a, __m128 b) __m128 _mm_cmpunord_ss(__m128 a, __m128 b) CMPSS for greater-than-or-equal__m128 _mm_cmpge_ss(__m128 a, __m128 b) CMPSS for not-greater-than-or-equal__m128 _mm_cmpnge_ss(__m128 a, __m128 b) CMPSS for not-less-than-or-equal__m128 _mm_cmpnle_ss(__m128 a, __m128 b) SIMD Floating-Point Exceptions Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table, Denormal....
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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