ia-32_instruction-set-ref_a-m

Is floating point value dest dest src fi if

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Unformatted text preview: k. The source operand is loaded without rounding errors. The sign of the source operand is preserved, including that of -0. The packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits (AH through FH). Attempting to load an invalid encoding produces an undefined result. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation TOP TOP - 1; ST(0) ConvertToDoubleExtendedPrecisionFP(SRC); FPU Flags Affected C1 C0, C2, C3 Set to 1 if stack overflow occurred; otherwise, set to 0. Undefined. Floating-Point Exceptions #IS Stack overflow occurred. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-292 Vol. 2 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-293 INSTRUCTION SET REFERENCE, A-M FBSTP--Store BCD Integer and Pop Opcode DF /6 Instruction FBSTP m80bcd 64-Bit Mode Valid Compat/ Leg Mode Valid Description Store ST(0) in m80bcd and pop ST(0). Description Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination operand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value, according to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The destination operand specifies the address where the first byte destination value is to be stored. The BCD value (including its sign bit) requi...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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