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#GP(0) #SS(0) #PF(fault-code) #NM #UD If the memory address is in a non-canonical form. If a memory address referencing the SS segment is in a noncanonical form. For a page fault (implementation specific). If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol. 2 3-559 INSTRUCTION SET REFERENCE, A-M MASKMOVQ--Store Selected Bytes of Quadword
Opcode 0F F7 /r Instruction MASKMOVQ mm1, mm2 64-Bit Mode Valid Compat/ Leg Mode Valid Description Selectively write bytes from mm1 to memory location using the byte mask in mm2. The default memory location is specified by DS:EDI. Description
Stores selected bytes from the source operand (first operand) into a 64-bit memory location. The mask operand (second operand) selects which bytes from the source operand are written to memory. The source and mask operands are MMX technology registers. The location of the first byte of the memory location is specified by DI/EDI and DS registers. (The size of the store address depends on the address-size attribute.) The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write. The MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-temporal hint is implemented by using a write combining (WC) memory type protocol (see "Caching of Temporal vs. Non-Temporal Data" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVEDQU instructions if multiple processors might use different memory types to read/write the destination memory locations. This instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). The behavior of the MASKMOVQ instruction with a mask of all 0s is as follows: No data will be written to memory. Transition from x87 FPU to MMX technology state will occur. Exceptions associated with addressing memory and page faults may still be signaled (implementation dependent). Signaling of breakpoints (code or data) is not guaranteed (implementation dependent). If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these memory types is not guaranteed (that is, is reserved) and is implementation-specific. 3-560 Vol. 2 INSTRUCTION SET REFERENCE, A-M The MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-by-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is to be written directly using the byte-mask without allocat...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11