Is not aligned on a 16 byte boundary regardless of

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Unformatted text preview: n Separates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0), and pushes the significand onto the register stack. Following this operation, the new top-of-stack register ST(0) contains the value of the original significand expressed as a floating-point value. The sign and significand of this value are the same as those found in the source operand, and the exponent is 3FFFH (biased value for a true exponent of zero). The ST(1) register contains the value of the original operand's true (unbiased) exponent expressed as a floatingpoint value. (The operation performed by this instruction is a superset of the IEEErecommended logb(x) function.) This instruction and the F2XM1 instruction are useful for performing power and range scaling operations. The FXTRACT instruction is also useful for converting numbers in double extended-precision floating-point format to decimal representations (e.g., for printing or displaying). If the floating-point zero-divide exception (#Z) is masked and the source operand is zero, an exponent value of is stored in register ST(1) and 0 with the sign of the source operand is stored in register ST(0). This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation TEMP Significand(ST(0)); ST(0) Exponent(ST(0)); TOP TOP - 1; ST(0) TEMP; FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred. Undefined. 3-426 Vol. 2 INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS #IA #Z #D Stack underflow or overflow occurred. Source operand is an SNaN value or unsupported format. ST(0) operand is 0. Source operand is a denormal value. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-427 INSTRUCTION SET REFERENCE, A-M FYL2X--Compute y log2x Opcode D9 F1 Instruction FYL2X 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(1) with (ST(1) log2ST(0)) and pop the register stack. Description Computes (ST(1) log2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source operand in ST(0) must be a non-zero positive number. The following table shows the results obtained when taking the log of various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-53. FYL2X Results ST(0) - - -F * * * * * * NaN 0 + ** * * ** - +0 < +F < +1 + +F +0 -0 -F - +1 * -0 -0 +0 +0 NaN +F > +1 - + - - NaN NaN NaN NaN NaN NaN NaN NaN * * * * * * NaN ST(1) -F -0 +0 +F + NaN -F -0 +0 +F + NaN * * + + NaN NaN NaN NOTES: F Means finite floating-point value. * Indicates floating-point invalid-operation (#IA) exception. ** Indicates floating-point z...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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