This preview shows page 1. Sign up to view the full content.
Unformatted text preview: ap gate is NULL. If the interrupt vector number is outside the IDT limits. If the interrupt vector number points to a gate which is in noncanonical space. If the interrupt vector number points to a descriptor which is not a 64-bit interrupt gate or 64-bit trap gate. If the descriptor pointed to by the gate selector is outside the descriptor table limit. If the descriptor pointed to by the gate selector is in non-canonical space. If the descriptor pointed to by the gate selector is not a code segment. If the descriptor pointed to by the gate selector doesn't have the L-bit set, or has both the L-bit and D-bit set. If the descriptor pointed to by the gate selector has DPL > CPL. 3-478 Vol. 2 INSTRUCTION SET REFERENCE, A-M #SS(0) #SS(selector) If a push of the old EFLAGS, CS selector, EIP, or error code is in non-canonical space with no stack switch. If a push of the old SS selector, ESP, EFLAGS, CS selector, EIP, or error code is in non-canonical space on a stack switch (either CPL change or no-CPL with IST). If the 64-bit interrupt-gate, 64-bit trap-gate, or code segment is not present. If an attempt to load RSP from the TSS causes an access to noncanonical space. If the RSP from the TSS is outside descriptor table limits. If a page fault occurs. #NP(selector) #TS(selector) #PF(fault-code) Vol. 2 3-479 INSTRUCTION SET REFERENCE, A-M INVD--Invalidate Internal Caches
Opcode* 0F 08 Instruction INVD 64-Bit Mode Valid Compat/ Leg Mode Valid Description Flush internal caches; initiate flushing of external caches. NOTES: * See the IA-32 Architecture Compatibility section below. Description
Invalidates (flushes) the processor's internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory. After executing this instruction, the processor does not wait for the external caches to complete their flushing operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush signal. The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction. Use this instruction with care. Data cached internally and not written back to main memory will be lost. Unless there is a specific requirement or benefit to flushing caches without writing back modified cache lines (for example, testing or fault recovery where cache coherency with main memory is not a concern), software should use the WBINVD instruction. This instruction's operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility
The INVD instruction is implementation dependent; it may be implemented differently on different families of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor. Operation
View Full Document
This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11