ia-32_instruction-set-ref_a-m

It is cleared the cf pf af sf and of flags are set

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: he current privilege level is 3. 3-150 Vol. 2 INSTRUCTION SET REFERENCE, A-M CMPXCHG8B/CMPXCHG16B--Compare and Exchange Bytes Opcode* 0F C7 /1 m64 Instruction CMPXCHG8B m64 64-Bit Mode Valid Compat/ Leg Mode Valid* Description Compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX. Compare RDX:RAX with m128. If equal, set ZF and load RCX:RBX into m128. Else, clear ZF and load m128 into RDX:RAX. REX.W + 0F C7 /1 m128 CMPXCHG16B m128 Valid N.E. NOTES: * See IA-32 Architecture Compatibility section below. Description Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand (destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX). The destination operand is an 8-byte memory location (or 16-byte memory location if operand size is 128 bits). For the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the loworder 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the high-order 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is written into the destination. (The processor never produces a locked read without also producing a locked write.) In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that CMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. See the summary chart at the beginning of this section for encoding data and limits. For information on the CPUID flag that indicates CMPXCHG16B, see page 3-172. IA-32 Architecture Compatibility This instruction encoding is not supported on Intel processors earlier than the Pentium processors. Vol. 2 3-151 INSTRUCTION SET REFERENCE, A-M Operation IF (64-Bit Mode and OperandSize = 64) THEN IF (RDX:RAX = DEST) ZF 1; DEST RCX:RBX; ELSE ZF 0; RDX:RAX DEST; FI ELSE IF (EDX:EAX = DEST) ZF 1; DEST ECX:EBX; ELSE ZF 0; EDX:EAX DEST; FI; FI; Flags Affected The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are unaffected. Protected Mode Exceptions #UD #GP(0) If the destination operand is not a memory location. If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault...
View Full Document

Ask a homework question - tutors are online