ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: double-precision floating-point value from m64 to high quadword of xmm. Move double-precision floating-point value from high quadword of xmm to m64. Description Moves a double-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be an XMM register or a 64-bit memory location. This instruction allows a double-precision floating-point value to be moved to and from the high quadword of an XMM register and memory. It cannot be used for register to register or memory to memory moves. When the destination operand is an XMM register, the low quadword of the register remains unchanged. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation MOVHPD instruction for memory to XMM move: DEST[127:64] SRC; (* DEST[63:0] unchanged *) MOVHPD instruction for XMM to memory move: DEST SRC[127:64]; Intel C/C++ Compiler Intrinsic Equivalent MOVHPD MOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p) void _mm_storeh_pd (double *p, __m128d a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. Vol. 2 3-621 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-622 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVHPS--Move High Packed Single-Precision Floating-Point Values 64Bit Mode Valid Opcode 0F 16 /r Instruction MOVHPS xmm, m64 MOVHPS m64, xmm Compat/ Leg Mode Valid 0F 17 /r Valid Valid Description Move two packed single-precision floating-point values from m64 to high quadword of xmm. Move two packed single-precision floating-point values from high quadword of xmm to m64. Description Moves two packed single-precision floating-po...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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