ia-32_instruction-set-ref_a-m

Mode load dword at address rsi into eax load qword at

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Unformatted text preview: ult occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-545 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-546 Vol. 2 INSTRUCTION SET REFERENCE, A-M LOOP/LOOPcc--Loop According to ECX Counter Opcode E2 cb REX.W + E2 cb E1 cb REX.W + E1 cb E0 cb REX.W + E0 cb Instructio n LOOP rel8 LOOP rel8 LOOPE rel8 LOOPE rel8 LOOPNE rel8 LOOPNZ rel8 64-Bit Mode Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid N.E. Valid N.E. Description Decrement count; jump short if count 0. Decrement 64-bit count in RCX; jump short if count 0. Decrement count; jump short if count 0 and ZF = 1. Decrement 64-bit count in RCX; jump short if count 0 and ZF = 1. Decrement count; jump short if count 0 and ZF = 0. Decrement 64-bit count in RCX; jump short if count 0 and ZF = 0. Description Performs a loop operation using the ECX or CX register as a counter. Each time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is 0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If the count is not zero, a near jump is performed to the destination (target) operand, which is presumably the instruction at the beginning of the loop. If the address-size attribute is 32 bits, the ECX register is used as the count register. Otherwise, the CX register is used. The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). This offset is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer. Offsets of 128 to +127 are allowed with this instruction. Some forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before the count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction to indicate the condition...
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