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Unformatted text preview: 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-296 Vol. 2 INSTRUCTION SET REFERENCE, A-M FCHS--Change Sign
Opcode D9 E0 Instruction FCHS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Complements sign of ST(0). Description
Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magnitude or vice versa. The following table shows the results obtained when changing the sign of various classes of numbers. Table 3-25. FCHS Results
- -F ST(0) DEST + +F +0 -0 -F
- NaN -0 +0 +F + NaN NOTES: * F means finite floating-point value. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation
SignBit(ST(0)) NOT (SignBit(ST(0))); FPU Flags Affected
C1 C0, C2, C3 Set to 0 if stack underflow occurred; otherwise, set to 0. Undefined. Floating-Point Exceptions
#IS Stack underflow occurred. Protected Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Vol. 2 3-297 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
Same exceptions as in Protected Mode. 3-298 Vol. 2 INSTRUCTION SET REFERENCE, A-M FCLEX/FNCLEX--Clear Exceptions
Opcode* 9B DB E2 Instruction FCLEX FNCLEX* 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clear floating-point exception flags after checking for pending unmasked floating-point exceptions. Clear floating-point exception flags without checking for pending unmasked floating-point exceptions. DB E2 Valid Valid NOTES: * See IA-32 Architecture Compatibility section below. Description
Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles any pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does not. The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception. IA-32 Architecture Compatibility
When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled "No-Wait FPU Instructions Can Get FPU Interrupt in Window" in Appendix D of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An FNCLEX inst...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11