ia-32_instruction-set-ref_a-m

Of segment if any part of the operand lies outside

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Unformatted text preview: emporal vs. Non-Temporal Data" in Chapter 10 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1. Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with the SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors might use different memory types to read/write the destination memory locations. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation DEST SRC; Intel C/C++ Compiler Intrinsic Equivalent MOVNTQ void_mm_stream_pi(__m64 * p, __m64 a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. Vol. 2 3-647 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM #MF #UD #AC(0) For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #MF #UD If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #MF #UD #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-648 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVQ--Move Quadword 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Opcode 0F 6F /r 0F 7F /r F3 0F 7E 66 0F D6 Instruction MOVQ mm, mm/m64 MOVQ mm/m64, mm MOVQ xmm1, xmm2/m64 MOVQ xmm2/m64, xmm1 Description Move quadword from mm/m64 to mm. Move quadword from mm to mm/m64. Move quadword from xmm2/mem64 to xmm1. Move quadword from xmm1 to xmm2/mem64. Description Copies a quadword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations. This instruction can be used to move a quadword between two MMX technology registers or between an MMX technology register and a 64-bit memory location, or to move data...
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