ia-32_instruction-set-ref_a-m

Of segment ss0 pffault code nm ud for an illegal

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Unformatted text preview: between two XMM registers or between an XMM register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations. When the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s. In 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15). Operation MOVQ instruction when operating on MMX technology registers and memory locations: DEST SRC; MOVQ instruction when source and destination operands are XMM registers: DEST[63:0] SRC[63:0]; MOVQ instruction when source operand is XMM register and destination operand is memory location: DEST SRC[63:0]; MOVQ instruction when source operand is memory location and destination operand is XMM register: DEST[63:0] SRC; DEST[127:64] 0000000000000000H; Vol. 2 3-649 INSTRUCTION SET REFERENCE, A-M Flags Affected None. SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM #MF #PF(fault-code) #AC(0) If CR0.TS[bit 3] = 1. (MMX register operations only) If there is a pending FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #UD If any part of the operand lies outside of the effective address space from 0 to FFFFH. If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM #MF If CR0.TS[bit 3] = 1. (MMX register operations only) If there is a pending FPU exception. 3-650 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If CR0.EM[bit 2] = 1. (XMM register operations only) If CR4.OSFXSR[bit 9] = 0. (XMM register operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM #MF #PF(fault-code) #AC(0) If CR0.TS[bit 3] = 1. (MMX regi...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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