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Unformatted text preview: f the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol. 2 3-565 INSTRUCTION SET REFERENCE, A-M MAXPS--Return Maximum Packed Single-Precision Floating-Point Values
Opcode 0F 5F /r Instruction MAXPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the maximum single-precision floating-point values between xmm2/m128 and xmm1. Description
Performs a SIMD compare of the packed single-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the maximum value for each pair of values to the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is returned. If a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN version of the SNaN is not returned). If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation
IF ((DEST[31:0] = 0.0) and (SRC[31:0] = 0.0)) THEN SRC[31:0]; ELSE IF (DEST[31:0] = SNaN) THEN SRC[31:0]; FI; ELSE IF SRC[31:0] = SNaN) THEN SRC[31:0]; FI; ELSE IF (DEST[31:0] > SRC[31:0]); FI; THEN DEST[31:0]; ELSE SRC[31:0]; FI; FI; (* Repeat operation for 2nd and 3rd doublewords *); DEST[31:0] DEST[127:64] IF ((DEST[127:96] = 0.0) and (SRC[127:96] = 0.0)) THEN SRC[127:96]; ELSE IF (DEST[127:96] = SNaN) THEN SRC[127:96]; ELSE IF SRC[127:96] = SNaN) THEN SRC[127:96]; ELSE IF (DEST[127:96] > SRC[127:96]) 3-566 Vol. 2 INSTRUCTION SET REFERENCE, A-M THEN DEST[127:96]; ELSE SRC[127:96]; FI; FI; Intel C/C++ Compiler Intrinsic Equivalent
MAXPS __m128d _mm_max_ps(__m128d a, __m128d b) SIMD Floating-Point Exceptions
Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #XM #UD If a memory operand effective address is outside the SS segment limit. F...
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- Winter '11