ia-32_instruction-set-ref_a-m

Old data prior to the store vol 2 3 557 instruction

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ing old data prior to the store. In 64-bit mode, the memory address is specified by DS:RDI. Operation IF (MASK[7] = 1) THEN DEST[DI/EDI] SRC[7:0] ELSE (* Memory location unchanged *); FI; IF (MASK[15] = 1) THEN DEST[DI/EDI +1] SRC[15:8] ELSE (* Memory location unchanged *); FI; (* Repeat operation for 3rd through 6th bytes in source operand *) IF (MASK[63] = 1) THEN DEST[DI/EDI +15] SRC[63:56] ELSE (* Memory location unchanged *); FI; Intel C/C++ Compiler Intrinsic Equivalent void_mm_maskmove_si64(__m64d, __m64n, char * p) Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments (even if mask is all 0s). If the destination operand is in a nonwritable segment. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #NM #MF #UD For an illegal address in the SS segment (even if mask is all 0s). For a page fault (implementation specific). If CR0.TS[bit 3] = 1. If there is a pending FPU exception. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If Mod field of the ModR/M byte not 11B #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #MF If any part of the operand lies outside the effective address space from 0 to FFFFH. (even if mask is all 0s). If CR0.TS[bit 3] = 1. If there is a pending FPU exception. Vol. 2 3-561 INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault (implementation specific). If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #MF #UD If the memory address is in a non-canonical form. If a memory address referencing the SS segment is in a noncanonical form. For a page fault (implementation specific). If CR0.TS[bit 3] = 1. If there is a pending FPU exception. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. If Mod field of the ModR/M byte not 11B #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-562 Vol. 2 INSTRUCTION SET REFERENCE, A-M MAXPD--Return Maximum Packed Double-Precision Floating-Point Values Opcode 66 0F 5F /r Instruction MAXPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the maximum doubleprecision floating-point values between xmm2/m128 and xmm1. Description Performs a SIMD compare of the packed double-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the maximum value for each pair of values to the destination operand. The source operand can be an XMM regis...
View Full Document

This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

Ask a homework question - tutors are online