Opcode reg field as registers 0 through 7 rex

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Unformatted text preview: Cases of REX Encodings ModR/M or SIB ModR/M Byte Sub-field Encodings Compatibility Mode Operation SIB byte present. Compatibility Mode Implications SIB byte required for ESP-based addressing. Additional Implications REX prefix adds a fourth bit (b) which is not decoded (don't care). SIB byte also required for R12-based addressing. REX prefix adds a fourth bit (b) which is not decoded (don't care). Using RBP or R13 without displacement must be done using mod = 01 with a displacement of 0. REX prefix adds a fourth bit (b) which is decoded. There are no additional implications. The expanded index field allows distinguishing RSP from R12, therefore R12 can be used as an index. REX prefix adds a fourth bit (b) which is not decoded. This requires explicit displacement to be used with EBP/RBP or R13. mod != 11 r/m == b*100(ESP) mod == 0 r/m == b*101(EBP) ModR/M Byte Base register not used. EBP without a displacement must be done using mod = 01 with displacement of 0. SIB Byte index == 0100(ESP) Index register not used. ESP cannot be used as an index register. SIB Byte base == 0101(EBP) Base register is unused if mod = 0. Base register depends on mod encoding. NOTES: * Don't care about the value of REX.B Displacement Addressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings. The ModR/M and SIB displacement sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits. Vol. 2 2-13 INSTRUCTION FORMAT Direct Memory-Offset MOVs In 64-bit mode, direct memory-offset forms of the MOV instruction are extended to specify a 64-bit immediate absolute address. This address is called a moffset. No prefix is needed to specify this 64-bit memory offset. For these MOV instructions, the size of the memory offset follows the address-size default (64 bits in 64-bit mode). See Table 2-6. Table 2-6. Direct Memory Offset Form of MOV Opcode A0 A1 A2 A3 Instruction MOV AL, moffset MOV EAX, moffset MOV moffset, AL MOV moffset, EAX Immediates In 64-bit mode, the typical size of immediate operands remains 32 bits. When the operand size is 64 bits, the processor sign-extends all immediates to 64 bits prior to their use. Support for 64-bit immediate operands is accomplished by expanding the semantics of the existing move (MOV reg, imm16/32) instructions. These instructions (opcodes B8H BFH) move 16-bits or 32-bits of immediate data (depending on the effective operand size) into a GPR. When the effective operand size is 64 bits, these instructions can be used to load an immediate into a GPR. A REX prefix is needed to override the 32-bit default operand size to a 64-bit operand size. For example: 48 B8 8877665544332211 MOV RAX,1122334455667788H RIP-Relative Addressing A new addressing form, RIP-relative (relative instruction-pointer) addressing, is implemented in 64-bit mode. An effective address is formed by adding displacement to the 64-bit RIP of the next instruction. In IA-32 architecture and compatibility mode, ad...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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