ia-32_instruction-set-ref_a-m

Operand and stores the result in the high quadword of

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: cts the single-precision floating-point value in the second dword of the source operand from the first dword of the source operand and stores the result in the third dword of the destination operand. Subtracts the single-precision floating-point value in the fourth dword of the source operand from the third dword of the source operand and stores the result in the fourth dword of the destination operand. See Figure 3-13. 3-444 Vol. 2 INSTRUCTION SET REFERENCE, A-M Figure 3-13. HSUBPS--Packed Single-FP Horizontal Subtract In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation xmm1[31:0] = xmm1[31:0] - xmm1[63:32]; xmm1[63:32] = xmm1[95:64] -xmm1[127:96]; xmm1[95:64] = xmm2/m128[31:0] - xmm2/m128[63:32]; xmm1[127:96] = xmm2/m128[95:64] - xmm2/m128[127:96]; Intel C/C++ Compiler Intrinsic Equivalent HSUBPS __m128 _mm_hsub_ps(__m128 a, __m128 b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Vol. 2 3-445 INSTRUCTION SET REFERENCE, A-M Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #NM #XM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM #UD If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. 3-446 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM #UD If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing...
View Full Document

Ask a homework question - tutors are online