Operand is a byte memory location the availability of

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Unformatted text preview: y ordered by the MFENCE instruction. It is not guaranteed to be ordered by any other fencing or serializing instructions or by another CLFLUSH instruction. For example, software can use an MFENCE instruction to insure that previous stores are included in the write-back. The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load (and in addition, a CLFLUSH instruction is allowed to flush a linear address in an execute-only segment). Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables. The CLFLUSH instruction was introduced with the SSE2 extensions; however, because it has its own CPUID feature flag, it can be implemented in IA-32 processors that do not include the SSE2 extensions. Also, detecting the presence of the SSE2 extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is implemented in the processor. CLFLUSH operation is the same in non-64-bit modes and 64-bit mode. Vol. 2 3-107 INSTRUCTION SET REFERENCE, A-M Operation Flush_Cache_Line(SRC); Intel C/C++ Compiler Intrinsic Equivalents CLFLUSH void_mm_clflush(void const *p) Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CPUID.01H:EDX.CLFSH[bit 19] = 0. Real-Address Mode Exceptions GP(0) #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CPUID.01H:EDX.CLFSH[bit 19] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CPUID.01H:EDX.CLFSH[bit 19] = 0. 3-108 Vol. 2 INSTRUCTION SET REFERENCE, A-M CLI -- Clear Interrupt Flag Opcode FA Instruction CLI 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clear interrupt flag; interrupts disabled when interrupt flag cleared. Description If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the CLI and STI instruction have no affect on the generation of exceptions and NMI interrupts. When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the EFLAGS register, leaving IF unaffected. Table 3-6 indicates the action of the CLI instruction depending on the processor operating mode and the CPL/IOPL of the running program or procedure. CLI operation is the same in non-64-bit modes and 64-bit mode. Table 3-6. Decision Table for CLI Results PE 0 1 1 1 1 1 1 1 VM X 0 0 0 0...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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