ia-32_instruction-set-ref_a-m

Operand of 1 this instruction can be used with a lock

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: in AL Quotient, AH Remainder. Unsigned divide AX by r/m8, with result stored in AL Quotient, AH Remainder. Unsigned divide DX:AX by r/m16, with result stored in AX Quotient, DX Remainder. Unsigned divide EDX:EAX by r/m32, with result stored in EAX Quotient, EDX Remainder. Unsigned divide RDX:RAX by r/m64, with result stored in RAX Quotient, RDX Remainder. REX + F6 /6 Valid N.E. F7 /6 DIV r/m16 Valid Valid F7 /6 DIV r/m32 Valid Valid REX.W + F7 /6 DIV r/m64 Valid N.E. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can be a generalpurpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor). Division using 64-bit operand is available only in 64-bit mode. Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in RAX, the remainder in RDX. See the summary chart at the beginning of this section for encoding data and limits. See Table 3-20. 3-262 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-20. DIV Action Operand Size Word/byte Doubleword/word Quadword/doubleword Doublequadword/ quadword Dividend AX DX:AX EDX:EAX RDX:RAX Divisor r/m8 r/m16 r/m32 r/m64 Quotient AL AX EAX RAX Remainder AH DX EDX RDX Maximum Quotient 255 65,535 232 - 1 264 - 1 Operation IF SRC = 0 THEN #DE; FI; (* Divide Error *) IF OperandSize = 8 (* Word/Byte Operation *) THEN temp AX / SRC; IF temp > FFH THEN #DE; (* Divide error *) ELSE AL temp; AH AX MOD SRC; FI; ELSE IF OperandSize = 16 (* Doubleword/word operation *) THEN temp DX:AX / SRC; IF temp > FFFFH THEN #DE; (* Divide error *) ELSE AX temp; DX DX:AX MOD SRC; FI; FI; ELSE IF Operandsize = 32 (* Quadword/doubleword operation *) THEN temp EDX:EAX / SRC; IF temp > FFFFFFFFH THEN #DE; (* Divide error *) ELSE EAX temp; EDX EDX:EAX MOD SRC; FI; FI; Vol. 2 3-263 INSTRUCTION SET REFERENCE, A-M ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *) THEN temp RDX:RAX / SRC; IF temp > FFFFFFFFFFFFFFFFH THEN #DE; (* Divide error *) ELSE RAX temp; RDX RDX:RAX MOD SRC; FI; FI; FI; Flags Affected The CF, OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #DE #GP(0) If the source operand (divisor) is 0 If the quotient is too large for the designated r...
View Full Document

Ask a homework question - tutors are online