ia-32_instruction-set-ref_a-m

Operand to the higher 32bits of each qword

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Unformatted text preview: ] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-669 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-670 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVSX/MOVSXD--Move with Sign-Extension 64-Bit Mode Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Valid N.E. N.E. Opcode 0F BE /r 0F BE /r REX + 0F BE /r 0F BF /r REX.W + 0F BF /r REX.W** + 63 /r Instruction MOVSX r16, r/m8 MOVSX r32, r/m8 MOVSX r64, r/m8* MOVSX r32, r/m16 MOVSX r64, r/m16 MOVSXD r64, r/m32 Description Move byte to word with sign-extension. Move byte to doubleword with sign-extension. Move byte to quadword with sign-extension. Move word to doubleword, with sign-extension. Move word to quadword with sign-extension. Move doubleword to quadword with signextension. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. ** The use of MOVSXD without REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using MOVSXD without REX.W. Description Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1). The size of the converted value depends on the operand-size attribute. In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation DEST SignExtend(SRC); Flags Affected None. Vol. 2 3-671 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mo...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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