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Unformatted text preview: INIT--Initialize Floating-Point Unit Opcode 9B DB E3 Instruction FINIT FNINIT* 64-Bit Mode Valid Compat/ Leg Mode Valid Description Initialize FPU after checking for pending unmasked floating-point exceptions. Initialize FPU without checking for pending unmasked floating-point exceptions. DB E3 Valid Valid NOTES: * See IA-32 Architecture Compatibility section below. Description Sets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU control word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared (no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all tagged as empty (11B). Both the instruction and data pointers are cleared. The FINIT instruction checks for and handles any pending unmasked floating-point exceptions before performing the initialization; the FNINIT instruction does not. The assembler issues two instructions for the FINIT instruction (an FWAIT instruction followed by an FNINIT instruction), and the processor executes each of these instructions in separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception. This instruction's operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNINIT instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled "No-Wait FPU Instructions Can Get FPU Interrupt in Window" in Appendix D of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An FNINIT instruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor. In the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear the instruction and data pointers. This instruction affects only the x87 FPU. It does not affect the XMM and MXCSR registers. 3-330 Vol. 2 INSTRUCTION SET REFERENCE, A-M Operation FPUControlWord 037FH; FPUStatusWord 0; FPUTagWord FFFFH; FPUDataPointer 0; FPUInstructionPointer 0; FPULastInstructionOpcode 0; FPU Flags Affected C0, C1, C2, C3 set to 0. Floating-Point Exceptions None. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-331 INSTRUCTION SET REFERENCE, A-M FIST/FISTP--Store Integer Opcode DF /2 DB /2 DF /3 DB /3 DF /7 Instruction FIST m16int FIST m32int FISTP m16int FISTP m32int FISTP m64int 64-Bit Mode Valid Valid V...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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