ia-32_instruction-set-ref_a-m

Or have undefined formats detection of a qnan value

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Unformatted text preview: Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-311 INSTRUCTION SET REFERENCE, A-M FDECSTP--Decrement Stack-Top Pointer Opcode D9 F6 Instruction FDECSTP 64-Bit Mode Valid Compat/ Leg Mode Valid Description Decrement TOP field in FPU status word. Description Subtracts one from the TOP field of the FPU status word (decrements the top-ofstack pointer). If the TOP field contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation IF TOP = 0 THEN TOP 7; ELSE TOP TOP 1; FI; FPU Flags Affected The C1 flag is set to 0. The C0, C2, and C3 flags are undefined. Floating-Point Exceptions None. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. 3-312 Vol. 2 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-313 INSTRUCTION SET REFERENCE, A-M FDIV/FDIVP/FIDIV--Divide Opcode D8 /6 DC /6 D8 F0+i DC F8+i DE F8+i DE F9 DA /6 DE /6 Instruction FDIV m32fp FDIV m64fp FDIV ST(0), ST(i) FDIV ST(i), ST(0) FDIVP ST(i), ST(0) FDIVP FIDIV m32int FIDIV m16int 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Description Divide ST(0) by m32fp and store result in ST(0). Divide ST(0) by m64fp and store result in ST(0). Divide ST(0) by ST(i) and store result in ST(0). Divide ST(i) by ST(0) and store result in ST(i). Divide ST(i) by ST(0), store result in ST(i), and pop the register stack. Divide ST(1) by ST(0), store result in ST(1), and pop the register stack. Divide ST(0) by m32int and store result in ST(0). Divide ST(0) by m64int and store result in ST(0). Description Divides the destination operand by the source operand and stores the result in the destination location. The destination operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format. The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0) register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location (either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by the contents of the ST(i) register o...
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