ia-32_instruction-set-ref_a-m

Or second operand be returned the action of minsd can

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Unformatted text preview: supported at privilege levels 1 through 3 (test for the appropriate support before unconditional use). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLES MSR; disabling MONITOR clears the CPUID feature flag and causes execution to generate an illegal opcode exception. The instruction's operation is the same in non-64-bit modes and 64-bit mode. 3-588 Vol. 2 INSTRUCTION SET REFERENCE, A-M Operation MONITOR sets up an address range for the monitor hardware using the content of EAX as an effective address and puts the monitor hardware in armed state. Always use memory of the write-back caching type. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are used to communicate other information to the monitor hardware. Intel C/C++ Compiler Intrinsic Equivalent MONITOR void _mm_monitor(void const *p, unsigned extensions,unsigned hints) Exceptions None Protected Mode Exceptions #GP(0) #GP(0) #SS(0) #PF(fault-code) #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For ECX has a value other than 0. For an illegal address in the SS segment. For a page fault (TBD). If CPUID.01H:ECX.MONITOR[bit 3] = 0. If executed at privilege level 1 through 3 when the instruction is not available. If LOCK, REP, REPNE/NZ and Operand Size override prefixes are used. Real Address Mode Exceptions #GP #GP(0) #UD If any part of the operand lies outside of the effective address space from 0 to FFFFH. For ECX has a value other than 0. If CPUID.01H:ECX.MONITOR[bit 3] = 0. If LOCK, REP, REPNE/NZ and Operand Size override prefixes are used. Virtual 8086 Mode Exceptions #GP #GP(0) If any part of the operand lies outside of the effective address space from 0 to FFFFH. For ECX has a value other than 0. Vol. 2 3-589 INSTRUCTION SET REFERENCE, A-M #UD If CPUID.01H:ECX.MONITOR[bit 3] = 0. If executed at privilege level 1 through 3 when the instruction is not available. If LOCK, REP, REPNE/NZ and Operand Size override prefixes are used. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If the memory address is in a non-canonical form. If ECX 0. #PF(fault-code) #UD For a page fault. If CPUID.01H:ECX.MONITOR[bit 3] = 0. If the F3H, F2H, 66H or LOCK prefix is used. 3-590 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOV--Move Opcode 88 /r REX + 88 /r 89 /r 89 /r REX.W + 89 /r 8A /r REX + 8A /r 8B /r 8B /r REX.W + 8B /r 8C /r REX.W + 8C /r Instruction MOV r/m8,r8 MOV r/m8***,r8*** MOV r/m16,r16 MOV r/m32,r32 MOV r/m64,r64 MOV r8,r/m8 MOV r8***,r/m8*** MOV r16,r/m16 MOV r32,r/m32 MOV r64,r/m64 MOV r/m16,Sreg** MOV r/m64,Sreg** 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid Valid N.E. Valid N.E. Valid Valid N.E. Valid Valid Description Move r8 to r/m8. Move r8 to r/m8. Move r16 to r/m16. M...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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