Promotes operation to 64 bits lodslodsq load the

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Unformatted text preview: being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag; the ZF flag is changed by other instructions in the loop. In 64-bit mode, use of the REX.W prefix enables 64 bit counts. JMP Short is RIP = RIP + 8-bit offset sign extended to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Vol. 2 3-547 INSTRUCTION SET REFERENCE, A-M Operation IF AddressSize = 32 THEN Count is ECX; ELSE IF AddressSize = 64 and REX.W used THEN Count is RCX FI; ELSE AddressSize = 16 THEN Count is CX; FI; Count Count 1; IF Instruction is not LOOP THEN IF (Instruction LOOPE) or (Instruction LOOPZ) THEN IF (ZF = 1) and (Count 0) THEN BranchCond 1; ELSE BranchCond 0; FI; ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ) IF (ZF = 0 ) and (Count 0) THEN BranchCond 1; ELSE BranchCond 0; FI; FI; ELSE (* Instruction = LOOP *) IF (Count 0) THEN BranchCond 1; ELSE BranchCond 0; FI; FI; IF BranchCond = 1 THEN IF OperandSize = 32 THEN EIP EIP + SignExtend(DEST); ELSE IF OperandSize = 64 THEN RIP RIP + SignExtend(DEST); FI; ELSE IF OperandSize = 16 THEN EIP EIP AND 0000FFFFH; FI; ELSE IF OperandSize = (32 or 64) THEN IF (R/E)IP < CS.Base or (R/E)IP > CS.Limit #GP; FI; 3-548 Vol. 2 INSTRUCTION SET REFERENCE, A-M FI; FI; ELSE Terminate loop and continue program execution at (R/E)IP; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the offset being jumped to is beyond the limits of the CS segment. Real-Address Mode Exceptions #GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override prefix is used. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the offset being jumped to is in a non-canonical form. Vol. 2 3-549 INSTRUCTION SET REFERENCE, A-M LSL--Load Segment Limit Opcode 0F 03 /r 0F 03 /r REX.W + 0F 03 /r Instruction LSL r16, r16/m16 LSL r32, r32/m161 LSL r64, r32/m161 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Description Load: r16 segment limit, selector r16/m16. Load: r32 segment limit, selector r32/m16. Load: r64 segment limit, selector r32/m16 NOTES: 1 For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored. Description Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. The destination operand is a general-purpose register. The processor performs access checks as part of the loading process. Once loaded in the destination register, software can compare the segment limit with the...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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