ia-32_instruction-set-ref_a-m

Reference is made while the current privilege level

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Unformatted text preview: quot; in Appendix D of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An FNSAVE instruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor. Operation (* Save FPU State and Registers *) DEST[FPUControlWord] FPUControlWord; DEST[FPUStatusWord] FPUStatusWord; DEST[FPUTagWord] FPUTagWord; DEST[FPUDataPointer] FPUDataPointer; DEST[FPUInstructionPointer] FPUInstructionPointer; DEST[FPULastInstructionOpcode] FPULastInstructionOpcode; DEST[ST(0)] ST(0); DEST[ST(1)] ST(1); DEST[ST(2)] ST(2); DEST[ST(3)] ST(3); DEST[ST(4)] ST(4); DEST[ST(5)] ST(5); DEST[ST(6)] ST(6); DEST[ST(7)] ST(7); (* Initialize FPU *) FPUControlWord 037FH; FPUStatusWord 0; FPUTagWord FFFFH; FPUDataPointer 0; FPUInstructionPointer 0; FPULastInstructionOpcode 0; 3-372 Vol. 2 INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The C0, C1, C2, and C3 flags are saved and then cleared. Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS #NM If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #NM #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-373 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-374 Vol. 2 INSTRUCTION SET REFERENCE, A-M FSCALE--Scale Opcode D9 FD Instruction FSCALE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Scale ST(0) by ST(1). Description Truncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of the destination operand. The destinati...
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