ia-32_instruction-set-ref_a-m

Ia-32_instruction-set-ref_a-m

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Unformatted text preview: XSAVE map. In 64-bit mode, all of the SSE 3-420 Vol. 2 INSTRUCTION SET REFERENCE, A-M registers, XMM0 through XMM15, are saved. But the layout of the 64-bit FXSAVE map has two flavors, depending on the value of the REX.W bit. The difference of these two flavors is in the FPU IP and FPU DP pointers. When REX.W = 0, the FPU IP is saved as CS with the 32 bit IP, and the FPU DP is saved as DS with the 32 bit DP. When REX.W = 1, the FPU IP and FPU DP are both 64 bit values without and segment selectors. The IA-32e mode save formats are shown in Table 3-51 and Table 3-52 listed below. Table 3-51. Layout of the 64-bit-mode FXSAVE Map with Promoted OperandSize 15 14 13 12 11 10 9 8 7 FOP MXCSR 6 5 FTW FPU DP ST0/MM0 ST1/MM1 ST2/MM2 ST3/MM3 ST4/MM4 ST5/MM5 ST6/MM6 ST7/MM7 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 Reserved Reserved 4 3 FSW 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 272 288 304 320 336 352 368 384 400 416 432 FPU IP MXCSR_MASK Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FCW Vol. 2 3-421 INSTRUCTION SET REFERENCE, A-M Table 3-51. Layout of the 64-bit-mode FXSAVE Map with Promoted OperandSize (Contd.) 15 14 13 12 11 10 9 8 7 Reserved Reserved Reserved Reserved 6 5 4 3 2 1 0 448 464 480 496 Table 3-52. Layout of the 64-bit-mode FXSAVE Map with Default OperandSize 15 14 13 CS 12 11 10 9 8 7 FOP Reserved 6 5 FTW DS ST0/MM0 ST1/MM1 ST2/MM2 ST3/MM3 ST4/MM4 ST5/MM5 ST6/MM6 ST7/MM7 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15 4 3 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 272 288 304 320 336 352 368 384 Reserved FPU IP MXCSR FSW FPU DP FCW MXCSR_MASK Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 400 3-422 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-52. Layout of the 64-bit-mode FXSAVE Map with Default OperandSize (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 416 432 448 464 480 496 Reserved Reserved Reserved Reserved Reserved Reserved Operation IF 64-Bit Mode THEN IF REX.W = 1 THEN DEST Save64BitPromotedFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR); ELSE DEST Save64BitDefaultFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR); FI; ELSE DEST SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR); FI; Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See the description of the alignment check exception [#AC] below.) #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If instruction is preceded by a LOCK override prefix. #AC If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16-byte boundary, as described above. If the alignment check Vol. 2 3-423 INSTRUCTION SET...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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