ia-32_instruction-set-ref_a-m

Register is being loaded and the segment pointed to

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Unformatted text preview: tel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, for more information about the behavior of this instruction in VMX non-root operation. Operation DEST SRC; Flags Affected The OF, SF, ZF, AF, PF, and CF flags are undefined. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. 3-598 Vol. 2 INSTRUCTION SET REFERENCE, A-M If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1). If an attempt is made to write a 1 to any reserved bit in CR4. If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading of a control register causes the PDPT to be loaded into the processor. Real-Address Mode Exceptions #GP If an attempt is made to write a 1 to any reserved bit in CR4. If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 when the PE flag is set to 0). Virtual-8086 Mode Exceptions #GP(0) These instructions cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions #GP(0) If the current privilege level is not 0. If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1). If an attempt is made to write a 1 to any reserved bit in CR3. If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5]. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1). Attempting to clear CR0.PG[bit 32]. If an attempt is made to write a 1 to any reserved bit in CR4. If an attempt is made to write a 1 to any reserved bit in CR8. If an attempt is made to write a 1 to any reserved bit in CR3. If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5]. Vol. 2 3-599 INSTRUCTION SET REFERENCE, A-M MOV--Move to/from Debug Registers Opcode 0F 21/r REX.W + 0F 21/r 0F 23 /r REX.W + 0F 23 /r Instruction MOV r32, DR0-DR7 MOV r64, DR0-DR7 MOV DR0-DR7,r32 MOV DR0-DR7,r64 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid N.E. Description Move debug register to r32 Move extended debug register to r64. Move r32 to debug register Move r64 to extended debug register. Description Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See Chapter 18, "Debugging and Performance Monitoring", of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for a detailed description of the flags and fields in the debug registers.) The instructions must be executed at privilege level 0 or i...
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