ia-32_instruction-set-ref_a-m

Register or memory location is multiplied by the

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Unformatted text preview: LSE CF 0; OF 0; FI; FI; FI; Flags Affected For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Vol. 2 3-455 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-456 Vol. 2 INSTRUCTION SET REFERENCE, A-M IN--Input from Port Opcode E4 ib E5 ib E5 ib EC ED ED Instruction IN AL, imm8 IN AX, imm8 IN EAX, imm8 IN AL,DX IN AX,DX IN EAX,DX 64-Bit Mode Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Description Input byte from imm8 I/O port address into AL. Input word from imm8 I/O port address into AX. Input dword from imm8 I/O port address into EAX. Input byte from I/O port in DX into AL. Input word from I/O port in DX into AX. Input doubleword from I/O port in DX into EAX. Description Copies the value from the I/O port specified with the second operand (source operand) to the destination operand (first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the DX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte immediate allows I/O p...
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