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Unformatted text preview: ; Continue (* Continue execution *) Flags Affected
None. 3-480 Vol. 2 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions
#GP(0) If the current privilege level is not 0. Real-Address Mode Exceptions
None. Virtual-8086 Mode Exceptions
#GP(0) The INVD instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
Same exceptions as in Protected Mode. Vol. 2 3-481 INSTRUCTION SET REFERENCE, A-M INVLPG--Invalidate TLB Entry
Opcode 0F 01/7 Instruction INVLPG m 64-Bit Mode Valid Compat/ Leg Mode Valid Description Invalidate TLB Entry for page that contains m. NOTES: * See the IA-32 Architecture Compatibility section below. Description
Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the source operand. The source operand is a memory address. The processor determines the page that contains that address and flushes the TLB entry for that page. The INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction. The INVLPG instruction normally flushes the TLB entry only for the specified page; however, in some cases, it flushes the entire TLB. See "MOV--Move to/from Control Registers" in this chapter for further information on operations that flush the TLB. This instruction's operation is the same in all non-64-bit modes. It also operates the same in 64-bit mode, except if the memory address is in non-canonical form. In this case, INVLPG is the same as a NOP. IA-32 Architecture Compatibility
The INVLPG instruction is implementation dependent, and its function may be implemented differently on different families of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor. Operation
Flush(RelevantTLBEntries); Continue; (* Continue execution *) Flags Affected
None. Protected Mode Exceptions
#GP(0) #UD If the current privilege level is not 0. Operand is a register. 3-482 Vol. 2 INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions
#UD Operand is a register. Virtual-8086 Mode Exceptions
#GP(0) The INVLPG instruction cannot be executed at the virtual-8086 mode. 64-Bit Mode Exceptions
#GP(0) #UD If the current privilege level is not 0. Operand is a register. Vol. 2 3-483 INSTRUCTION SET REFERENCE, A-M IRET/IRETD--Interrupt Return
Opcode CF CF REX.W + CF Instruction IRET IRETD IRETQ 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description Interrupt return (16-bit operand size). Interrupt return (32-bit operand size). Interrupt return (64-bit operand size). Description
Returns program control from an exception or interrupt handler to a program or procedure that was interrupted by an exception, an external interrupt, or a softwaregenerated interrupt. These instructions are also used to perform a return from a nested task. (A nested task is created when...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11