ia-32_instruction-set-ref_a-m

Rounding control bits in the mxcsr register if a

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Unformatted text preview: . Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. Vol. 2 3-195 INSTRUCTION SET REFERENCE, A-M #NM #XM #UD If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-196 Vol. 2 INSTRUCTION SET REFERENCE, A-M CVTPD2PI--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F 2D /r Instruction CVTPD2PI mm, xmm/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values from xmm/m128 to two packed signed doubleword integers in mm. Description Converts two packed double-precision floating-point values in the source operand (second operand) to two packed signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned. This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]); DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]); Intel C/C++ Compiler Intrinsic Equivalent CVTPD1PI __m64 _mm_cvtpd_pi32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Vol. 2 3-197 INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #PF(fault-code) #MF #NM #XM #UD For an illegal address in the SS segment. For a page fault. If there is a pending x87 FPU exception. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10]...
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