ia-32_instruction-set-ref_a-m

Second operand and returns the minimum value for each

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Unformatted text preview: d floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] IF ((DEST[63:0] = 0.0) and (SRC[63:0] = 0.0)) THEN SRC[63:0]; ELSE IF (DEST[63:0] = SNaN) THEN SRC[63:0]; FI; ELSE IF SRC[63:0] = SNaN) THEN SRC[63:0]; FI; ELSE IF (DEST[63:0] < SRC[63:0]) THEN DEST[63:0]; ELSE SRC[63:0]; FI; FI; (* DEST[127:64] is unchanged *); Intel C/C++ Compiler Intrinsic Equivalent MINSD __m128d _mm_min_sd(__m128d a, __m128d b) 3-582 Vol. 2 INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #XM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand effective address is outside the SS segment limit. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #XM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Vol. 2 3-583 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-584 Vol. 2 INSTRUCTION SET REFERENCE, A-M MINSS--Return Minimum Scalar Single-Precision Floating-Point Value Opcode F3 0F 5D /r Instruction MINSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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