ia-32_instruction-set-ref_a-m

See chapter 18 debugging and performance monitoring in

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Unformatted text preview: terrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability. 28 29 30 31 HTT TM Reserved PBE INPUT EAX = 2: Cache and TLB Information Returned in EAX, EBX, ECX, EDX When CPUID executes with EAX set to 2, the processor returns information about the processor's internal caches and TLBs in the EAX, EBX, ECX, and EDX registers. The encoding is as follows: The least-significant byte in register EAX (register AL) indicates the number of times the CPUID instruction must be executed with an input value of 2 to get a complete description of the processor's caches and TLBs. The first member of the family of Pentium 4 processors will return a 1. The most significant bit (bit 31) of each register indicates whether the register contains valid information (set to 0) or is reserved (set to 1). If a register contains valid information, the information is contained in 1 byte descriptors. Table 3-17 shows the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache or TLB types. The descriptors may appear in any order. 3-176 Vol. 2 INSTRUCTION SET REFERENCE, A-M Table 3-17. Encoding of Cache and TLB Descriptors Descriptor Value 00H 01H 02H 03H 04H 05H 06H 08H 0AH 0BH 0CH 22H 23H 25H 29H 2CH 30H 40H 41H 42H 43H 44H 45H 46H 47H 49H Null descriptor Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries Instruction TLB: 4 MByte pages, 4-way set associative, 2 entries Data TLB: 4 KByte pages, 4-way set associative, 64 entries Data TLB: 4 MByte pages, 4-way set associative, 8 entries Data TLB1: 4 MByte pages, 4-way set associative, 32 entries 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rdlevel cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size 2nd-lev...
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