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Selector fi switch tasks to tss if eip not within

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Unformatted text preview: L from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate. If the upper type field of a 64-bit call gate is not 0x0. If the segment selector from a 64-bit call gate is beyond the descriptor table limits. If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the L-bit set and the D-bit clear. If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it is a code segment. If the code segment is non-confirming and CPL DPL. If the code segment is confirming and CPL < DPL. #NP(selector) #UD #PF(fault-code) #AC(0) If a code segment or 64-bit call gate is not present. (64-bit mode only) If a far jump is direct to an absolute address in memory. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-510 Vol. 2 INSTRUCTION SET REFERENCE, A-M LAHF--Load Status Flags into AH Register Opcode 9F Instruction LAHF 64-Bit Mode Invalid* Compat/ Leg Mode Valid Description Load: AH EFLAGS(SF:ZF:0:AF:0:PF:1:CF). NOTES: * Valid in specific steppings. See Description section. Description Moves the low byte of the EFLAGS register (which includes status flags SF, ZF, AF, PF, and CF) to the AH register. Reserved bits 1, 3, and 5 of the EFLAGS register are set in the AH register as shown in the "Operation" section below. This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1. Operation IF 64-Bit Mode THEN IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1; THEN AH RFLAGS(SF:ZF:0:AF:0:PF:1:CF); ELSE #UD; FI; ELSE AH EFLAGS(SF:ZF:0:AF:0:PF:1:CF); FI; Flags Affected None. The state of the flags in the EFLAGS register is not affected. Protected Mode Exceptions None. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions None. Vol. 2 3-511 INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions None. 64-Bit Mode Exceptions #UD If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0. 3-512 Vol. 2 INSTRUCTION SET REFERENCE, A-M LAR--Load Access Rights Byte Opcode 0F 02 /r 0F 02 /r REX.W + 0F 02 /r Instruction LAR r16, r16/m16 LAR r32, r32/m161 LAR r64, r32/m161 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description r16 r16/m16 masked by FF00H. r32 r32/m16 masked by 00FxFF00H r64 r32/m16 masked by 00FxFF00H and zero extended NOTES: 1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored. Description Loads the access rights from the segment descriptor specified by the second operand (source operand) into the first operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a register or a memory location) contains the segment selector for the segment descriptor being accessed. If the source operand is a memory address, only 16 bits of data are accessed. The destination ope...
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  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

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