ia-32_instruction-set-ref_a-m

Stack pointer top by 1 the nooperand version of the

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Unformatted text preview: e. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-403 INSTRUCTION SET REFERENCE, A-M FTST--TEST Opcode D9 E4 Instruction FTST 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare ST(0) with 0.0. Description Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). Table 3-45. FTST Results Condition ST(0) > 0.0 ST(0) < 0.0 ST(0) = 0.0 Unordered C3 0 0 1 1 C2 0 0 0 1 C0 0 1 0 1 This instruction performs an "unordered comparison." An unordered comparison also checks the class of the numbers being compared (see "FXAM--ExamineModR/M" in this chapter). If the value in register ST(0) is a NaN or is in an undefined format, the condition flags are set to "unordered" and the invalid operation exception is generated. The sign of zero is ignored, so that ( 0.0 +0.0). This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation CASE (relation of operands) OF Not comparable: C3, C2, C0 111; ST(0) > 0.0: C3, C2, C0 000; ST(0) < 0.0: C3, C2, C0 001; ST(0) = 0.0: C3, C2, C0 100; ESAC; FPU Flags Affected C1 C0, C2, C3 Set to 0 if stack underflow occurred; otherwise, set to 0. See Table 3-45. 3-404 Vol. 2 INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS #IA #D Stack underflow occurred. The source operand is a NaN value or is in an unsupported format. The source operand is a denormal value. Protected Mode Exceptions #NM #MF CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-405 INSTRUCTION SET REFERENCE, A-M FUCOM/FUCOMP/FUCOMPP--Unordered Compare Floating Point Values Opcode DD E0+i DD E1 DD E8+i DD E9 DA E9 Instruction FUCOM ST(i) FUCOM FUCOMP ST(i) FUCOMP FUCOMPP 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Description Compare ST(0) with ST(i). Compare ST(0) with ST(1). Compare ST(0) with ST(i) and pop register stack. Compare ST(0) with ST(1) and pop register stack. Compare ST(0) with ST(1) and pop register stack twice. Description Performs an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2, and C3 in the FPU status word according to the results (see the...
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