ia-32_instruction-set-ref_a-m

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Unformatted text preview: 1. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If instruction is preceded by a LOCK prefix. #AC If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16byte boundary, as described above. If the alignment check exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments). Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE2[bit 26] = 0. If instruction is preceded by a LOCK override prefix. 3-414 Vol. 2 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC For a page fault. For unaligned memory reference. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #MF #PF(fault-code) #NM #UD If there is a pending x87 FPU exception. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0. If instruction is preceded by a LOCK prefix. #AC If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16-byte boundary, as described above. If the alignment check exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignment check exception might be signaled for a 2-byte misalignment, whereas a general protection exception might be signaled for all other misalignments (4-, 8-, or 16-byte misalignments). Vol. 2 3-415 INSTRUCTION SET REFERENCE, A-M FXSAVE--Save x87 FPU, MMX Technology, SSE, and SSE2 State Opcode 0F AE /0 Instruction FXSAVE m512byte 64-Bit Mode Valid Compat/ Leg Mode Valid Description Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte. Description Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte mem...
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