ia-32_instruction-set-ref_a-m

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Unformatted text preview: links are: 1-8 Vol. 2 CHAPTER 2 INSTRUCTION FORMAT This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for IA-32e mode and its submodes are described in Section 2.2. 2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), primary opcode bytes (up to three bytes), an addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), and an immediate data field (if required). Instruction Prefixes Up to four prefixes of 1 byte each (optional) Opcode ModR/M SIB 1 byte (if required) Displacement Address displacement of 1, 2, or 4 bytes or none 3 2 0 Immediate Immediate data of 1, 2, or 4 bytes or none 1-, 2-, or 3-byte 1 byte opcode (if required) 7 6 5 3 2 0 7 6 5 Mod Reg/ Opcode R/M Scale Index Base Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format Vol. 2 2-1 INSTRUCTION FORMAT 2.1.1 Instruction Prefixes Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, one prefix may be used from each of four groups (Groups 1, 2, 3, 4) and be placed in any order. Group 1 -- Lock and repeat prefixes: F0H--LOCK F2H--REPNE/REPNZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as a mandatory prefix for some SIMD instructions) F3H--REP or REPE/REPZ (used only with string instructions; when used with the escape opcode 0FH, this prefix is treated as an mandatory prefix for some SIMD instructions) Group 2 -- Segment override prefixes: 2EH--CS segment override (use with any branch instruction is reserved) 36H--SS segment override prefix (use with any branch instruction is reserved) 3EH--DS segment override prefix (use with any branch instruction is reserved) 26H--ES segment override prefix (use with any branch instruction is reserved) 64H--FS segment override prefix (use with any branch instruction is reserved) 65H--GS segment override prefix (use with any branch instruction is reserved) 2EH--Branch not taken (used only with Jcc instructions) 3EH--Branch taken (used only with Jcc instructions) 66H--Operand-size override prefix (when used with the escape opcode 0FH, this is treated as a mandatory prefix for some SIMD instructions) 67H--Address-size override prefix -- Branch hints: Group 3 Group 4 2-2 Vol. 2 INSTRUCTION FORMAT The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared memory in a multiprocessor environment. See "LOCK--Assert LOCK# Signal Prefix" in Chapter 3, "Instruction Set Reference, A-M," for a description of this prefix. Repeat prefixes (F2H, F3H) caus...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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