ia-32_instruction-set-ref_a-m

That underflow does not occur table 3 54 fyl2xp1

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Unformatted text preview: nmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). Vol. 2 3-433 INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM #UD If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID feature flag SSE3 is 0. 3-434 Vol. 2 INSTRUCTION SET REFERENCE, A-M HADDPS--Packed Single-FP Horizontal Add Opcode F2 0F 7C /r Instruction HADDPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Horizontal add packed singleprecision floating-point values from xmm2/m128 to xmm1. Description Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand. Adds single-precision floating-point values in the third and fourth dword of the destination operand and stores the result in the second dword of the destination operand. Adds single-precision floating-point values in the first and second dword of the source operand and stores the result in the third dword of the destination operand. Adds single-precision floating-point values in the third and fourth dword of the source operand and stores the result in the fourth dword of the destination operand. See Figure 3-11. Figure 3-11. HADDPS--Packed Single-FP Horizontal Add Vol. 2 3-435...
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