ia-32_instruction-set-ref_a-m

The correct destination register and that the source

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Unformatted text preview: Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #XM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP(0) #NM If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. 3-146 Vol. 2 INSTRUCTION SET REFERENCE, A-M #XM #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-147 INSTRUCTION SET REFERENCE, A-M CMPXCHG--Compare and Exchange Opcode 0F B0/r Instruction CMPXCHG r/m8, r8 64-Bit Mode Valid Compat/ Leg Mode Valid* Description Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL. Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL. Compare AX with r/m16. If equal, ZF is set and r16 is loaded into r/m16. Else, clear ZF and load r/m16 into AX. Compare EAX with r/m32. If equal, ZF is set and r32 is loaded into r/m32. Else, clear ZF and load r/m32 into EAX. Compare RAX with r/m64. If equal, ZF is set and r64 is loaded into r/m64. Else, clear ZF and load r/m64 into RAX. REX + 0F B0/r CMPXCHG r/m8**,r8 Valid N.E. 0F B1/r CMPXCHG r/m16, r16 Valid Valid* 0F B1/r CMPXCHG r/m32, r32 Valid Valid* REX.W + 0F B1/r CMPXCHG r/m64, r64 Valid N.E. NOTES: * See the IA-32 Architecture Compatibility section below. ** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Compares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If t...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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