{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}


The description of ia 32 instructions started in

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: eloper's Manual, Volume 2B. Chapter 5 -- VMX Instruction Reference. Describes the virtual-machine extensions (VMX) of IA-32 instructions. VMX is intended to support virtualization of processor hardware and a system software layer acting as a host to multiple guest software environments. Appendix A -- Opcode Map. Gives an opcode map for the IA-32 instruction set. Appendix B -- Instruction Formats and Encodings. Gives the binary encoding of each form of each IA-32 instruction. Appendix C -- Intel C/C++ Compiler Intrinsics and Functional Equivalents. Lists the Intel C/C++ compiler intrinsics and their assembly code equivalents for each of the IA-32 MMX and SSE/SSE2/SSE3 instructions. 1.3 NOTATIONAL CONVENTIONS This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. A review of this notation makes the manual easier to read. 1.3.1 Bit and Byte Order In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. IA-32 processors are "little endian" machines; this means the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions. Vol. 2 1-3 ABOUT THIS MANUAL Highest Address 31 24 23 Data Structure 8 7 16 15 0 28 24 20 16 12 8 4 0 Bit offset Byte 3 Byte 2 Byte 1 Byte 0 Lowest Address Byte Offset Figure 1-1. Bit and Byte Order 1.3.2 Reserved Bits and Software Compatibility In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits: Do not depend on the states of any reserved bits when testing the values of registers which contain such bits. Mask out the reserved bits before testing. Do not depend on the states of any reserved bits when storing to memory or to a register. Do not depend on the ability to retain information written into any reserved bits. When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register. NOTE Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors. 1-4 Vol. 2 ABOUT THIS MANUAL 1.3.3 Instruction Operands When instructions are represented symbolically...
View Full Document

  • Winter '11
  • Watlins
  • X86, Intel corporation, Packed Single-Precision Floating-Point, Packed Double-Precision Floating-Point, single-precision floating-point values

{[ snackBarMessage ]}

Ask a homework question - tutors are online