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Unformatted text preview: ruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor. This instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point exception flags in the MXCRS register. This instruction's operation is the same in non-64-bit modes and 64-bit mode. Operation
FPUStatusWord[0:7] 0; FPUStatusWord 0; Vol. 2 3-299 INSTRUCTION SET REFERENCE, A-M FPU Flags Affected
The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are undefined. Floating-Point Exceptions
None. Protected Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Real-Address Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
Same exceptions as in Protected Mode. 3-300 Vol. 2 INSTRUCTION SET REFERENCE, A-M FCMOVcc--Floating-Point Conditional Move
Opcode* DA C0+i DA C8+i DA D0+i DA D8+i DB C0+i DB C8+i DB D0+i DB D8+i Instruction FCMOVB ST(0), ST(i) FCMOVE ST(0), ST(i) FCMOVBE ST(0), ST(i) FCMOVU ST(0), ST(i) FCMOVNB ST(0), ST(i) FCMOVNE ST(0), ST(i) FCMOVNBE ST(0), ST(i) FCMOVNU ST(0), ST(i) 64Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode* Valid Valid Valid Valid Valid Valid Valid Valid Description Move if below (CF=1). Move if equal (ZF=1). Move if below or equal (CF=1 or ZF=1). Move if unordered (PF=1). Move if not below (CF=0). Move if not equal (ZF=0). Move if not below or equal (CF=0 and ZF=0). Move if not unordered (PF=0). NOTES: * See IA-32 Architecture Compatibility section below. Description
Tests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination operand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Description column above and in Chapter 7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1. The source operand is always in the ST(i) register and the destination operand is always ST(0). The FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching overhead for IF operations and the possibility of branch mispredictions by the processor. A processor may not support the FCMOVcc instructions. Software can check if the FCMOVcc instructions are supported by checking the processor's feature information with the CPUID instruction (see "COMISS--Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS" in this chapter). If both the CMOV and FPU feature bits are set, the FCMOVcc instructions are supported. This instruction's operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility
The FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not available in earlier IA-32 processors. Vol. 2 3...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.
- Winter '11