ia-32_instruction-set-ref_a-m

The source operand if the content source operand is 0

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Unformatted text preview: contains a NULL segment selector. #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP #SS If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand effective address is outside the SS segment limit. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-71 INSTRUCTION SET REFERENCE, A-M BSWAP--Byte Swap Opcode 0F C8+rd REX.W + 0F C8+rd Instruction BSWAP r32 BSWAP r64 64-Bit Mode Valid* Valid Compat/ Leg Mode Valid N.E. Description Reverses the byte order of a 32-bit register. Reverses the byte order of a 64-bit register. NOTES: * See IA-32 Architecture Compatibility section below. Description Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting little-endian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG instruction. When the BSWAP instruction references a 16-bit register, the result is undefined. In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. IA-32 Architecture Legacy Compatibility The BSWAP instruction is not supported on IA-32 processors earlier than the Intel486TM processor family. For compatibility with this instruction, software should include functionally equivalent code for execution on Intel processors earlier than the Intel486 processor family. Operation TEMP DEST IF 64-bit mode AND OperandSize = 64 THEN DEST[7:0] TEMP[63:56]; DEST[15:8] TEMP[55:48]; DEST[23:16] TEMP[47:40]; DEST[31:24] TEMP[39:32]; DEST[39:32] TEMP[31:24]; DEST[47:40] TEMP[23:16]; DEST[55:48] TEMP[15:8]; DEST[63:56] TEMP[7:0]; ELSE DEST[7:0] TEMP[31:24]; DEST[15:8] TEMP[23:16]; 3-72 Vol. 2 INSTRUCTION SET REFERENCE, A-M DEST[23:16] TEMP[15:8]; DEST[31:24] TEMP[7:0]; FI; Flags Affected None. Exceptions (All Operating Modes) None. Vol. 2 3-73 INSTRUCTION SET REFERENC...
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