ia-32_instruction-set-ref_a-m

The source operand is a memory operand it must be

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Unformatted text preview: ECX.SSE3[bit 0] = 0. Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM If TS bit in CR0 is 1. For an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1. 3-46 Vol. 2 INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM #XM #UD If CR0.TS[bit 3] = 1. For an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1. If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) #NM #XM #UD For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Vol. 2 3-47 INSTRUCTION SET REFERENCE, A-M ADDSUBPS--Packed Single-FP Add/Subtract Opcode F2 0F D0 /r Instruction ADDSUBPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add/subtract single-precision floating-point values from xmm2/m128 to xmm1. Description Adds odd-numbered single-precision floating-point values of the source operand (second operand) with the corresponding single-precision floating-point values from the destination operand (first operand); stores the result in the odd-numbered values of the destination operand. Subtracts the even-numbered single-precision floating-point values in the source operand from the corresponding single-precision floating values in the destination operand; stores the result into the even-numbered values of the destination operand. The source operand can be a 128-bit memory location or an XMM register. The destination operand is an XMM register. See Figure 3-4. Figure 3-4. ADDSUBPS--Packed Single-FP Add/Subtract In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15). 3-48 Vol. 2 INSTRUCTION SET REFERENCE, A-M Operation xmm1[31:0] = xmm1[31:0] - xmm2/m128[31:0]; xmm1[63:32] = xmm1[63:32] + xmm2/m128[63:32]; xmm1[95:64] = xmm1[95:...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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