This preview shows page 1. Sign up to view the full content.
Unformatted text preview: d an unaligned memory reference is made. Compatibility Mode Exceptions
Same exceptions as in Protected Mode. 64-Bit Mode Exceptions
#SS(0) #GP(0) #NM #MF #PF(fault-code) #AC(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. CR0.EM[bit 2] or CR0.TS[bit 3] = 1. If there is a pending x87 FPU exception. If a page fault occurs. If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-399 INSTRUCTION SET REFERENCE, A-M FSUBR/FSUBRP/FISUBR--Reverse Subtract
Opcode D8 /5 DC /5 D8 E8+i DC E0+i DE E0+i Instruction FSUBR m32fp FSUBR m64fp FSUBR ST(0), ST(i) FSUBR ST(i), ST(0) FSUBRP ST(i), ST(0) 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Description Subtract ST(0) from m32fp and store result in ST(0). Subtract ST(0) from m64fp and store result in ST(0). Subtract ST(0) from ST(i) and store result in ST(0). Subtract ST(i) from ST(0) and store result in ST(i). Subtract ST(i) from ST(0), store result in ST(i), and pop register stack. Subtract ST(1) from ST(0), store result in ST(1), and pop register stack. Subtract ST(0) from m32int and store result in ST(0). Subtract ST(0) from m16int and store result in ST(0). DE E1 FSUBRP Valid Valid DA /5 DE /5 FISUBR m32int FISUBR m16int Valid Valid Valid Valid Description
Subtracts the destination operand from the source operand and stores the difference in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format. These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions. They are provided to support more efficient coding. The no-operand version of the instruction subtracts the contents of the ST(1) register from the ST(0) register and stores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents of a memory location (either a floating-point or an integer value) and stores the result in ST(0). The twooperand version, subtracts the contents of the ST(i) register from the ST(0) register or vice versa. The FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point reverse subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP. 3-400 Vol. 2 INSTRUCTION SET REFERENCE, A-M The FISUBR instructions convert an integer source operand to double extendedprecision floating-point format before performing the subtraction. The following table...
View Full Document
- Winter '11