ia-32_instruction-set-ref_a-m

To store the contents of an xmm register into a 128

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Unformatted text preview: / Leg Mode Valid Opcode F2 0F D6 Instruction MOVDQ2Q mm, xmm Description Move low quadword from xmm to mmx register. Description Moves the low quadword from the source operand (second operand) to the destination operand (first operand). The source operand is an XMM register and the destination operand is an MMX technology register. This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST SRC[63:0]; Intel C/C++ Compiler Intrinsic Equivalent MOVDQ2Q __m64 _mm_movepi64_pi64 ( __m128i a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-617 INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-618 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVHLPS-- Move Packed Single-Precision Floating-Point Values High to Low 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode OF 12 /r Instruction MOVHLPS xmm1, xmm2 Description Move two packed singleprecision floating-point values from high quadword of xmm2 to low quadword of xmm1. Description Moves two packed single-precision floating-point values from the high quadword of the source operand (second operand) to the low quadword of the destination operand (first operand). The high quadword of the destination operand is left unchanged. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation DEST[63:0] SRC[127:64]; (* DEST[127:64] unchanged *) Intel C/C++ Compiler Intrinsic Equivalent MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real Address Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-619 INSTRUCTION SET REFERENCE, A-M Virtual 8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-620 Vol. 2 INSTRUCTION SET REFERENCE, A-M MOVHPD--Move High Packed Double-Precision Floating-Point Value 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 66 0F 16 /r 66 0F 17 /r Instruction MOVHPD xmm, m64 MOVHPD m64, xmm Valid Valid Description Move...
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