ia-32_instruction-set-ref_a-m

Value in xmm1 description converts a single precision

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Unformatted text preview: If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. Vol. 2 3-231 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #XM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-232 Vol. 2 INSTRUCTION SET REFERENCE, A-M CVTSS2SI--Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer Opcode F3 0F 2D /r Instruction CVTSS2SI r32, xmm/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32. Convert one single-precision floating-point value from xmm/m32 to one signed quadword integer in r64. REX.W + F3 0F 2D /r CVTSS2SI r64, xmm/m32 Valid N.E. Description Converts a single-precision floating-point value in the source operand (second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (first operand). The source operand can be an XMM register or a memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single-precision floatingpoint value is contained in the low doubleword of the register. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned. In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the instruction to 64-bit operands. See the summary chart at the beginning of this section for encoding data and limits. Operation IF 64-bit Mode and OperandSize = 64 THEN DEST[64:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]); ELSE DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]); FI; Intel C/C++ Compiler Intrinsic Equivalent int_mm_cvtss_si32(__m128d a) Vol. 2 3-233 INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #XM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3]...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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