ia-32_instruction-set-ref_a-m

Void mmstorehpi m64 p m128d a simd floating point

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Unformatted text preview: . Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol. 2 3-629 INSTRUCTION SET REFERENCE, A-M MOVLPS--Move Low Packed Single-Precision Floating-Point Values Opcode 0F 12 /r Instruction MOVLPS xmm, m64 MOVLPS m64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move two packed single-precision floating-point values from m64 to low quadword of xmm. Move two packed single-precision floating-point values from low quadword of xmm to m64. 0F 13 /r Valid Valid Description Moves two packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand). The source and destination operands can be an XMM register or a 64-bit memory location. This instruction allows two single-precision floating-point values to be moved to and from the low quadword of an XMM register and memory. It cannot be used for register to register or memory to memory moves. When the destination operand is an XMM register, the high quadword of the register remains unchanged. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation MOVLPD instruction for memory to XMM move: DEST[63:0] SRC; (* DEST[127:64] unchanged *) MOVLPD instruction for XMM to memory move: DEST SRC[63:0]; Intel C/C++ Compiler Intrinsic Equivalent MOVLPS MOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p) void _mm_storel_pi (__m64 *p, __m128 a) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. 3-630 Vol. 2 INSTRUCTION SET REFERENCE, A-M #SS(0) #PF(fault-code) #NM #UD For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonica...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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