ia-32_instruction-set-ref_a-m

With a segment override prefix but the es segment

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Unformatted text preview: escription Moves a scalar double-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations. This instruction can be used to move a double-precision floating-point value to and from the low quadword of an XMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations. When the source and destination operands are XMM registers, the high quadword of the destination operand remains unchanged. When the source operand is a memory location and destination operand is an XMM registers, the high quadword of the destination operand is cleared to all 0s. In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15). Operation MOVSD instruction when source and destination operands are XMM registers: DEST[63:0] SRC[63:0]; (* DEST[127:64] unchanged *) MOVSD instruction when source operand is XMM register and destination operand is memory location: DEST SRC[63:0]; MOVSD instruction when source operand is memory location and destination operand is XMM register: DEST[63:0] SRC; DEST[127:64] 0000000000000000H; Vol. 2 3-659 INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent MOVSD MOVSD MOVSD __m128d _mm_load_sd (double *p) void _mm_store_sd (double *p, __m128d a) __m128d _mm_store_sd (__m128d a, __m128d b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #NM #UD For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. For an illegal address in the SS segment. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) #NM #UD If any part of the operand lies outside the effective address space from 0 to FFFFH. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) #AC(0) For a page fault. If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 3-660 Vol. 2 INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) #GP(0) #PF(fault-code) #NM #UD If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. For a page fault. If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is...
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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