ia-32_volume1_basic-arch

11 5 packed double precision floating point

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Unformatted text preview: . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 SHUFPD Instruction, Packed Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 UNPCKHPD Instruction, High Unpack and Interleave Operation . . . . . . . . . . . . . . . 11-11 UNPCKLPD Instruction, Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . 11-12 SSE and SSE2 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Example Masked Response for Packed Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 Asymmetric Processing in ADDSUBPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Horizontal Data Movement in HADDPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 xviii Vol. 1 CONTENTS PAGE Figure 12-3. Figure 13-1. Figure 13-2. Figure D-1. Figure D-2. Figure D-3. Figure D-4. Figure D-5. Figure D-6. Figure E-1. Horizontal Data Movement in PHADDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Memory-Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 I/O Permission Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6 Recommended Circuit for MS-DOS Compatibility x87 FPU Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7 Behavior of Signals During x87 FPU Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . D-8 Timing of Receipt of External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9 Arithmetic Example Using Infinity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-13 General Program Flow for DNA Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-26 Program Flow for a Numeric Exception Dispatch Routine . . . . . . . . . . . . . . . . . . . . . .D-27 Control Flow for Handling Unmasked Floating-Point Exceptions . . . . . . . . . . . . . . . . . E-6 Vol. 1 xix CONTENTS PAGE TABLES Table 2-1. Table 2-2. Table 2-3. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-10. Table 4-9. Table 4-11. Table 5-1. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 8-9. Table 8-10. Table 8-11. Table 9-1. Table 9-2. Table 9-3. Table 10-1. Table 11-1. Table 11-2. Key Features of Most Recent IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Key Features of Most Recent Intel 64 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Key Features of Previous Generations of IA-32 Processors . . ....
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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