ia-32_volume1_basic-arch

8 4 example x87 fpu dot product computation

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Unformatted text preview: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Moving the Condition Codes to the EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Contents of x87 FPU Opcode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Protected Mode x87 FPU State Image in Memory, 32-Bit Format . . . . . . . . . . . . . . 8-16 Real Mode x87 FPU State Image in Memory, 32-Bit Format . . . . . . . . . . . . . . . . . . . 8-16 Protected Mode x87 FPU State Image in Memory, 16-Bit Format . . . . . . . . . . . . . . 8-17 Real Mode x87 FPU State Image in Memory, 16-Bit Format . . . . . . . . . . . . . . . . . . . 8-17 x87 FPU Data Type Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 MMX Technology Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 MMX Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Data Types Introduced with the MMX Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 SIMD Execution Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 SSE Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 XMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 MXCSR Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 128-Bit Packed Single-Precision Floating-Point Data Type. . . . . . . . . . . . . . . . . . . . . 10-8 Packed Single-Precision Floating-Point Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 Scalar Single-Precision Floating-Point Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 SHUFPS Instruction, Packed Shuffle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 UNPCKHPS Instruction, High Unpack and Interleave Operation. . . . . . . . . . . . . . . . 10-15 UNPCKLPS Instruction, Low Unpack and Interleave Operation . . . . . . . . . . . . . . . . 10-15 Steaming SIMD Extensions 2 Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Data Types Introduced with the SSE2 Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Packed Double-Precision Floating-Point Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Scalar Double-Precision Floating-Point Operations . ....
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