ia-32_volume1_basic-arch

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Unformatted text preview: . . . . . . . . .D-12 D.3.2.2 Software Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-14 D.3.3 Synchronization Required for Use of x87 FPU Exception Handlers . . . . . . . . . . . . . . . .D-15 D.3.3.1 Exception Synchronization: What, Why and When . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-16 D.3.3.2 Exception Synchronization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-17 D.3.3.3 Proper Exception Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-17 D.3.4 x87 FPU Exception Handling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-18 D.3.5 Need for Storing State of IGNNE# Circuit If Using x87 FPU and SMM . . . . . . . . . . . . . .D-22 D.3.6 Considerations When x87 FPU Shared Between Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . .D-23 D.3.6.1 Speculatively Deferring x87 FPU Saves, General Overview . . . . . . . . . . . . . . . . . . . .D-24 D.3.6.2 Tracking x87 FPU Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-25 D.3.6.3 Interaction of x87 FPU State Saves and Floating-Point Exception Association . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-25 D.3.6.4 Interrupt Routing From the Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-28 D.3.6.5 Special Considerations for Operating Systems that Support Streaming SIMD Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-28 D.4 DIFFERENCES FOR HANDLERS USING NATIVE MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-29 D.4.1 Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387 Processors . . . .D-29 D.4.2 Changes with Intel486, Pentium and Pentium Pro Processors with CR0.NE[bit 5] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-30 D.4.3 Considerations When x87 FPU Shared Between Tasks Using Native Mode . . . . . . . . .D-30 APPENDIX E GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS E.1 TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.2 SOFTWARE EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.3 EXCEPTION SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3 E.4 SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754 . . . . . . . . . . . . . . . . . . E-4 E.4.1 Floating-Point Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
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This note was uploaded on 10/01/2013 for the course CPE 103 taught by Professor Watlins during the Winter '11 term at Mississippi State.

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